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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Bus Operations
Bus Operations
Table 2:
Bus Operations – Asynchronous Mode
Mode
Read
Write
Standby
No operation
Configuration
Power
Active
Active
Standby
Idle
Active
CLK 1
L
L
L
L
L
ADV#
L
L
X
X
L
CE#
L
L
H
L
L
OE#
L
X
X
X
H
WE#
H
L
X
X
L
CRE
L
L
L
L
H
LB#/
UB#
L
L
X
X
X
WAIT 2
Low-Z
Low-Z
High-Z
Low-Z
Low-Z
DQ[15:0] 3
Data-Out
Data-In
High-Z
X
High-Z
Notes
4
4
5, 6
4, 6
Register
DPD
Deep
L
X
H
X
X
X
X
High-Z
High-Z
7
power-down
Table 3:
Bus Operations – Burst Mode
Mode
Async read
Async write
Standby
No operation
Initial burst
Power
Active
Active
Standby
Idle
Active
CLK 1
L
L
L
L
ADV#
L
L
X
X
L
CE#
L
L
H
L
L
OE#
L
X
X
X
X
WE#
H
L
X
X
H
CRE
L
L
L
L
L
LB#/
UB#
L
L
X
X
L
WAIT 2
Low-Z
Low-Z
High-Z
Low-Z
Low-Z
DQ[15:0] 3
Data-Out
Data-In
High-Z
X
X
Notes
4
4
5, 6
4, 6
4, 8
read
Initial burst
Active
L
L
H
L
L
X
Low-Z
X
4, 8
write
Burst
Active
H
L
X
X
X
L
Low-Z
Data-In or
4, 8
continue
Data-Out
Burst suspend
Configuration
Active
Active
X
X
L
L
L
H
H
X
L
L
H
X
X
Low-Z
Low-Z
High-Z
High-Z
4, 8
8
register
DPD
Deep
L
X
H
X
X
X
X
High-Z
High-Z
7
power-down
Notes:
1. CLK must be LOW during async read and async write modes, and to achieve standby power
during standby and DPD modes. CLK must be static (HIGH or LOW) during burst suspend.
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in
select mode, DQ[7:0] are affected. When only UB# is in the select mode, DQ[15:8] are
affected.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally
isolated from any external influence.
6. V IN = V CC Q or 0V; all device balls must be static (unswitched) in order to achieve standby cur-
rent.
7. DPD is maintained until RCR is reconfigured.
8. Burst mode operation is initialized through the bus configuration register (BCR[15]).
PDF: 09005aef81cb58ed/Source: 09005aef81c7a667
16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2005 Micron Technology, Inc. All rights reserved.
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